Design and Analysis of MAC Unit Using Single Precision Floating Point Vedic Multiplier
By: Athira, A . D
.
Contributor(s): Krishnan, Anjaly.
Publisher: New Delhi STM Journals 2018Edition: Vol, 8(3), Sep-Dec.Description: 28-35p.Subject(s): EXTC EngineeringOnline resources: Click Here
In:
Journal of VLSI design tools & technology (JoVDTT)Summary: Multiplication and accumulation are the basic operations which are important in several microprocessors and digital signal processing (DSP) applications to execute dedicated algorithms. Developing high speed MAC is essential for real time DSP application. The MAC unit determines the speed of the overall system and it lies in the critical path. As the demand for high speed design is continuously increasing, the studies related to the field of multipliers and adders are endless and still significant. Multiplication of floating point numbers gives high resolution and has found extensive use in DSP applications. The critical part in single precision floating point multiplication is the 24×24 bit mantissa calculation. The speed of the system can be improved by enhancing the speed of multiplication. In this study, a 24 bit Vedic multiplier has been proposed using 3×3 Vedic multiplier as its basic block. This study proposes MAC unit using modified single precision floating point Vedic multiplier using 'Urdhava-Triyakbhyam' sutra. In this work, MAC unit for DSP application using 32 bit modified single precision floating point Vedic multiplier is simulated in Xilinx ISE 14.7 using Virtex 6 FPGA.
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School of Engineering & Technology Archieval Section | Not for loan | 2021-2021743 |
Multiplication and accumulation are the basic operations which are important in several microprocessors and digital signal processing (DSP) applications to execute dedicated algorithms. Developing high speed MAC is essential for real time DSP application. The MAC unit determines the speed of the overall system and it lies in the critical path. As the demand for high speed design is continuously increasing, the studies related to the field of multipliers and adders are endless and still significant. Multiplication of floating point numbers gives high resolution and has found extensive use in DSP applications. The critical part in single precision floating point multiplication is the 24×24 bit mantissa calculation. The speed of the system can be improved by enhancing the speed of multiplication. In this study, a 24 bit Vedic multiplier has been proposed using 3×3 Vedic multiplier as its basic block. This study proposes MAC unit using modified single precision floating point Vedic multiplier using 'Urdhava-Triyakbhyam' sutra. In this work, MAC unit for DSP application using 32 bit modified single precision floating point Vedic multiplier is simulated in Xilinx ISE 14.7 using Virtex 6 FPGA.
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